A NAND-type flash memory is widespread as a storage device for a large volume of data. At present, memory cells are miniaturized for cost reduction and capacity increase per bit. Further miniaturization in the future is demanded. However, further miniaturization of the flash memory involves many problems to be solved, such as the development of lithography technology, a short channel effect, inter-element interference, and the inhibition of inter-element variations. Therefore, there is a strong possibility that future continuous improvement of storage density only by the development of simple in-plane miniaturization technology is difficult.
Accordingly, there has been suggested a three-dimensional stacked layer type semiconductor memory as a new technique for increasing capacity that does not rely on the miniaturization of the lithography technology. The advantage of this three-dimensional stacked layer type semiconductor memory is that memory cells can be formed into a three-dimensional configuration without a substantial increase of processes and that a high memory capacity can be obtained at low cost.
A memory cell of the three-dimensional stacked layer type semiconductor memory that is generally used is a silicon/oxide/nitride/oxide/silicon (SONOS) type. The problems in putting the SONOS type memory cell into practical use include the improvement of writing/erasing characteristics and cycling resistance. That is, improving the writing/erasing characteristics and the cycling resistance is important in putting the three-dimensional stacked layer type semiconductor memory that uses the SONOS type memory cell into practical use.
Our intensive studies on this point have proved that in order to improve the above-mentioned characteristics, the composition of silicon nitride, when used as a charge storage layer, is preferably closer to the excess of silicon (silicon-rich SiN) than a stoichiometric composition.
However, silicon-rich SiN is said to have a relatively shallow in-film trap level, and it is known that trapped electrons are apt to diffuse because of, for example, hopping conduction between trap levels. In the meantime, charge storage layers of memory cells are physically combined in the three-dimensional stacked layer type semiconductor memory.
Therefore, the problem caused when the three-dimensional stacked layer type semiconductor memory is formed by the SONOS type memory cells that use silicon-rich SiN for the charge storage layers is the loss of data because of the diffusion of electrons injected into the charge storage layer of a memory cell to the charge storage layer of another adjacent memory cell.
This can be prevented by the charge storage layers structured to be independent for the respective memory cells in a memory cell array of the three-dimensional stacked layer type semiconductor memory.
If such a new device structure and a manufacturing method to obtain this structure are developed, the three-dimensional stacked layer type semiconductor memory can use, as the charge storage layer, an insulator such as silicon-rich SiN that is expected to be improved in characteristics, and can also use, as the charge storage layer, a conductor as an electrically floating gate.